About:
Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Author:
phase1geo [contact developer]

Rating:	reset 1 2 3 4 5 6 7 8 9 10
(not rated)

Homepage:
http://covered.sourceforge.net/
Tar/GZ:
http://prdownloads.sourceforge.net/covered/covered-0.6.1.tar.gz?download

Trove categories: [change]

[Development Status]		5 - Production/Stable
[Environment]		Console (Text Based)
[Intended Audience]		Developers
[License]		OSI Approved :: GNU General Public License (GPL)
[Operating System]		OS Independent
[Programming Language]		C, Tcl
[Topic]		Scientific/Engineering :: Electronic Design Automation (EDA)

Dependencies: [change]
No dependencies filed

 Branches

Branch	Version	Last release	License	URLs
Default	0.6.1	14-Mar-2008	GNU General Public License (GPL)
Development	20080530	30-May-2008	GNU General Public License (GPL)