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DOLPHIN SMASH

Changes: This release implements extended capabilities for mixed-signal interface devices, hierarchical tolerances on different nets or parts of the circuit, optimized Verilog-A behavioral model handling, input and output of .VEC digital vector files, and verification of PSL properties using the simple subset with mixed-signal extensions. Theis release also includes an optimized SPICE library parser for ten-fold reduction of circuit loading time when using statistical model parameter sets.

Changes: The release implements multi-core aware equation evaluation for SPICE device models to speed up the analog simulation, automatic detection of multiple operating points to ensure design operation for all bias points, simplified use of audio data files to drive analog simulation, time precision handling for VHDL and VHDL-AMS simulations longer than 9223 seconds, an enhanced debugger with expression watches, expression breakpoints and breakpoint actions, and user selection of which SPICE device and model parameters to output to the operating-point file.

Changes: A number of fixes to simulator control file parsing for mixed language netlists along with other simulator kernel corrections.

Changes: The release implements enhanced ease of setup with a simulator control file for analog and logic designers, a streamlined graphic user interface with reworked menu bar and enriched tool bars, integrated Power-Up analysis for transient ramp-up of circuit power supplies, accelerated automatic operating-point searching, bias point saving during transient analysis, noise analysis for Verilog-A models, encryption of SPICE libraries, and optimized on-the-fly SDF annotation to reduce memory consumption during circuit elaboration.

Changes: This release has a number of SPICE, Verilog, VHDL, and VHDL-AMS related bugfixes and minor improvements.