FSMDesigner
FSMDesigner is a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. It uses the Simple-Moore FSM model, guaranteeing efficient fast complex control circuits. It features graphical design of FSMs, support for automatic default transitions, validation of FSMs, a well-defined XML file format, generation of RTL HDL output for both Verilog and VHDL, full scriptability in Python, a modern GUI with undo and redo, simulation mode support, and table based data manipulation.
| Tags | Scientific/Engineering Electronic Design Automation (EDA) |
|---|---|
| Licenses | GPLv2 |
| Operating Systems | POSIX Linux |
| Implementation | C++ |
| Translations | English |
Recent releases
- 25 Apr 2008 10:50
Changes: This version improves several parts and introduces some new features. The main new features are SVG export and System Verilog Assertions (SVA) support for verification. This makes it possible, for example, to get a coverage analysis of your FSM simulation. Improvements include fixes in printing and mnenonic map generation.
- 03 Dec 2007 10:18
Changes: This version incorporates many build related improvements as well as more intuitive property editing. The configure script now actually tests for required librariess and programs; the property widget immediately updates the FSM view. Building has been tested on OpenSuSE 10.2 and 10.3.
- 24 Nov 2007 16:26
No changes have been submitted for this release.
