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About:
GEZEL is a language and open environment for exploration, simulation, and implementation of cycle-true hardware models. The models can be simulated stand-alone, or cosimulated with one of the supported instruction set simulators. GEZEL models can be automatically translated into VHDL for hardware synthesis targeting FPGA or ASIC.
Author:
Patrick Schaumont [contact developer]
Homepage:
http://rijndael.ece.vt.edu/gezel2
Tar/GZ:
http://rijndael.ece.vt.edu/gezel2/download/gezel-2.1.tar.gz
Trove categories:
[change]
Dependencies:
[change]
No dependencies filed
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